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| ADVANCED LINEAR DEVICES, INC. ALD110808/ALD110808A/ALD110908/ALD110908A VGS(th)= +0.8V e TM EPAD EN (R) AB LE D QUAD/DUAL N-CHANNEL ENHANCEMENT MODE EPAD(R) MATCHED PAIR MOSFET ARRAY GENERAL DESCRIPTION ALD110808A/ALD110808/ALD110908A/ALD110908 are monolithic quad/ dual N-Channel MOSFETs matched at the factory using ALD's proven EPAD(R) CMOS technology. These devices are intended for low voltage, small signal applications. These MOSFET devices are built on the same monolithic chip, so they exhibit excellent temperature tracking characteristics. They are versatile as circuit elements and are useful design component for a broad range of analog applications. They are basic building blocks for current sources, differential amplifier input stages, transmission gates, and multiplexer applications. For most applications, connect V- and N/C pins to the most negative voltage potential in the system and V+ pin to the most positive voltage potential (or left open unused). All other pins must have voltages within these voltage limits. ALD110808/ALD110908 devices are built for minimum offset voltage and differential thermal response, and they are suited for switching and amplifying applications in +1.0V to +10V (+/- 5 V) systems where low input bias current, low input capacitance and fast switching speed are desired. As these are MOSFET devices, they feature very large (almost infinite) current gain in a low frequency, or near DC, operating environment. These devices are suitable for use in precision applications which require very high current gain, beta, such as current mirrors and current sources. The high input impedance and the high DC current gain of the Field Effect Transistors result from extremely low current loss through the control gate. The DC current gain is limited by the gate input leakage current, which is specified at 30pA at room temperature. For example, DC beta of the device at a drain current of 3mA and input leakage current of 30pA at 25C is = 3mA/30pA = 100,000,000. FEATURES * Enhancement-mode (normally off) * Standard Gate Threshold Voltages: +0.8V * Matched MOSFET to MOSFET characteristics * Tight lot to lot parametric control * Low input capacitance * VGS(th) match to 2mV and 10mV * High input impedance -- 1012 typical * Positive,zero, and negative VGS(th) temperature coefficient * DC current gain >108 * Low input and output leakage currents ORDERING INFORMATION Operating Temperature Range* 0C to +70C 0C to +70C 16-Pin Plastic Dip Package ALD110808APC ALD110808 PC 16-Pin SOIC Package 8-Pin Plastic Dip Package 8Pin SOIC Package APPLICATIONS * Precision current mirrors * Precision current sources * Voltage choppers * Differential amplifier input stage * Voltage comparator * Voltage bias circuits * Sample and Hold * Analog inverter * Level shifters * Source followers and buffers * Current multipliers * Analog switches / multiplexers PIN CONFIGURATION ALD110808 N/C* GN1 DN1 S12 VDN4 GN4 N/C* 1 2 3 4 5 6 7 8 VVVM4 M3 M1 M2 V- V- 16 15 14 N/C* GN2 DN2 V+ S34 DN3 GN3 N/C* V+ 13 12 11 10 9 PC, SC PACKAGES ALD110908 VV- N/C* 1 2 3 4 8 7 N/C* GN1 DN1 S12 GN2 DN2 V- M1 M2 6 V5 PA, SA PACKAGES *N/C pins are internally connected. Connect to V- to reduce noise ALD110808ASC ALD110908APA ALD110908ASA ALD110808SC ALD110908PA ALD110908SA * Contact factory for industrial or military temp. ranges or user-specified threshold voltage values. Rev 1.0-0506 (c)2 005 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286 www.aldinc.com ABSOLUTE MAXIMUM RATINGS Drain-Source voltage, VDS Gate-Source voltage, VGS Power dissipation Operating temperature range PA, SA, PC, SC package Storage temperature range Lead temperature, 10 seconds 10.6V 10.6V 500 mW 0C to +70C -65C to +150C +260C OPERATING ELECTRICAL CHARACTERISTICS V+ = +5V (or open) V- = GND TA = 25C unless otherwise specified CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. ALD110808A / ALD110908A Parameter Gate Threshold Voltage Symbol VGS(th) Min 0.78 Typ 0.80 Max 0.82 ALD110808/ ALD110908 Min 0.78 Typ 0.80 Max 0.82 Unit V Test Condition IDS =1A VDS = 0.1V IDS=1A Offset Voltage VGS1-VGS2 VGS1-VGS2 Tempco VOS 1 2 3 10 mV VOS 5 -1.7 0.0 +1.6 12.0 3.0 5 -1.7 0.0 +1.6 12.0 3.0 V/ C VDS1= VDS2 ID= 1A ID= 20A VDS = 0.1V ID= 40A VGS= +10.3V VGS= +4.8V VDS= +5V VGS = +4.8V VDS = +9.8V GateThreshold Tempco VGS(th) IDS (ON) mV/ C mA On Drain Current Forward Transconductance GFS 1.4 1.4 mmho Transconductance Mismatch Output Conductance GFS GOS 1.8 68 1.8 68 % mho VGS =+4.8V VDS = +9.8V VDS = 0.1V VGS = +4.8V Drain Source On Resistance RDS (ON) 500 500 Drain Source On Resistance Mismatch Drain Source Breakdown Voltage Drain Source Leakage Current1 RDS (ON) 0.5 0.5 % BVDSX 10 10 V IDS = 1.0A VGS = -0.2V VGS = -0.2V VDS =10V, TA = 125C VDS = 0V VGS = 10V TA =125C IDS (OFF) IGSS 10 100 4 30 1 10 100 4 30 1 pA nA pA nA pF pF ns ns dB Gate Leakage Current1 3 3 Input Capacitance Transfer Reverse Capacitance Turn-on Delay Time Turn-off Delay Time Crosstalk Notes: 1 CISS CRSS ton toff 2.5 0.1 10 10 60 2.5 0.1 10 10 60 V+ = 5V RL= 5K V+ = 5V RL= 5K f = 100KHz Consists of junction leakage currents ALD110808/ALD110808A/ALD110908/ALD110908A Advanced Linear Devices 2 |
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